Electronics
VLSI
VLSI design and chip-level project titles.
Showing 59 projects
| Code | Title | Enquire |
|---|---|---|
| LOW POWER | ||
| ENV2401 | A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging | |
| ENV2402 | Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture | |
| ENV2403 | Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding | |
| ENV2404 | A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture for Low-Energy Consumption | |
| ENV2405 | Resource-Efficient SRAM-based Ternary Content Addressable Memory | |
| ENV2406 | Write-Amount-Aware Management Policies for STT-RAM Caches | |
| ENV2407 | Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA | |
| ENV2408 | High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder | |
| ENV2409 | High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations | |
| ENV2410 | Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST | |
| ENV2411 | Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map | |
| ENV2412 | Efficient Designs of Multi-ported Memory on FPGA | |
| ENV2413 | High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA | |
| ENV2414 | An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock | |
| ENV2415 | A 2.4-3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique | |
| ENV2416 | Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares | |
| ENV2417 | Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm | |
| ENV2418 | A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission | |
| ENV2419 | Scalable Device Array for Statistical Characterization of BTI-Related Parameters | |
| AREA EFFICIENT/ TIMING & DELAY REDUCTION | ||
| ENV2420 | VLSI Design of 64bit x 64bit High Performance Multiplier with Redundant Binary Encoding | |
| ENV2421 | ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware | |
| ENV2422 | Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs | |
| ENV2423 | Efficient Soft Cancelation Decoder Architectures for Polar Codes | |
| ENV2424 | Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition | |
| ENV2425 | Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication | |
| ENV2426 | FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers | |
| ENV2427 | Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields | |
| ENV2428 | Antiwear Leveling Design for SSDs With Hybrid ECC Capability | |
| ENV2429 | Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems Audio, Image and Video Processing | |
| ENV2430 | A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding | |
| ENV2431 | RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing | |
| ENV2432 | Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations | |
| ENV2433 | Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers | |
| ENV2434 | An FPGA-Based Hardware Accelerator for Traffic Sign Detection | |
| ENV2435 | Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations | |
| ENV2436 | Time-Encoded Values for Highly Efficient Stochastic Circuits | |
| ENV2437 | Design of Power and Area Efficient Approximate Multipliers VERIFICATION | |
| VERIFICATION | ||
| ENV2438 | COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits | |
| ENV2439 | Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction NETWORKING | |
| NETWORKING | ||
| ENV2440 | Multicast-Aware High-Performance Wireless Network-on-Chip Architectures | |
| ENV2441 | Temporarily Fine-Grained Sleep Technique for Near- and Sub-threshold Parallel Architectures | |
| ENV2442 | Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique | |
| ENV2443 | 10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage | |
| ENV2444 | Delay Analysis for Current Mode Threshold Logic Gate Designs | |
| ENV2445 | Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications | |
| ENV2446 | Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating | |
| ENV2447 | A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications | |
| ENV2448 | A 0.1-2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS | |
| ENV2449 | Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application | |
| ENV2450 | An All-MOSFET Sub-1-V Voltage Reference With a-51-dB PSR up to 60 MHz | |
| ENV2451 | A 65-nm CMOS Constant Current Source with Reduced PVT Variation | |
| ENV2452 | A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy | |
| ENV2453 | Preweighted Linearized VCO Analog-to-Digital Converter | |
| ENV2454 | A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression | |
| ENV2455 | Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template | |
| ENV2456 | On Micro-architectural Mechanisms for Cache Wear out Reduction | |
| ENV2457 | Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology | |
| ENV2458 | A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma-Delta Modulator Using Dynamically Biased Op Amp Sharing | |
| ENV2459 | A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures | |