| Project Code | VLSI Project Titles |
Lang/Year |
LOW POWER |
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ENV2401 |
A 2.5-ps Bin Size and 6.7-ps Resolution FPGA Time-to-Digital Converter Based on Delay Wrapping and Averaging | VLSI/2017 |
ENV2402 |
Coordinate Rotation-Based Low Complexity K-Means Clustering Architecture | VLSI/2017 |
ENV2403 |
Low-Power Scan-Based Built-In Self-Test Based on Weighted Pseudorandom Test Pattern Generation and Reseeding | VLSI/2017 |
ENV2404 |
A Way-Filtering-Based Dynamic Logical-Associative Cache Architecture for Low-Energy Consumption | VLSI/2017 |
ENV2405 |
Resource-Efficient SRAM-based Ternary Content Addressable Memory | VLSI/2017 |
ENV2406 |
Write-Amount-Aware Management Policies for STT-RAM Caches | VLSI/2017 |
ENV2407 |
Fault Diagnosis Schemes for Low-Energy Block Cipher Midori Benchmarked on FPGA | VLSI/2017 |
ENV2408 |
High-Throughput and Energy-Efficient Belief Propagation Polar Code Decoder | VLSI/2017 |
ENV2409 |
High-Speed Parallel LFSR Architectures Based on Improved State-Space Transformations | VLSI/2017 |
ENV2410 |
Scalable Approach for Power Droop Reduction During Scan-Based Logic BIST | VLSI/2017 |
ENV2411 |
Stochastic Implementation and Analysis of Dynamical Systems Similar to the Logistic Map | VLSI/2017 |
ENV2412 |
Efficient Designs of Multi-ported Memory on FPGA | VLSI/2017 |
ENV2413 |
High-Speed and Low-Latency ECC Processor Implementation Over GF(2m) on FPGA | VLSI/2017 |
ENV2414 |
An On-Chip Monitoring Circuit for Signal-Integrity Analysis of 8-Gb/s Chip-to-Chip Interfaces With Source-Synchronous Clock | VLSI/2017 |
ENV2415 |
A 2.4-3.6-GHz Wideband Sub-harmonically Injection-Locked PLL with Adaptive Injection Timing Alignment Technique | VLSI/2017 |
ENV2416 |
Hardware-Efficient Built-In Redundancy Analysis for Memory With Various Spares | VLSI/2017 |
ENV2417 |
Fast Automatic Frequency Calibrator Using an Adaptive Frequency Search Algorithm | VLSI/2017 |
ENV2418 |
A High-Efficiency 6.78-MHz Full Active Rectifier with Adaptive Time Delay Control for Wireless Power Transmission | VLSI/2017 |
ENV2419 |
Scalable Device Array for Statistical Characterization of BTI-Related Parameters | VLSI/2017 |
AREA EFFICIENT/ TIMING & DELAY REDUCTION |
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ENV2420 |
VLSI Design of 64bit x 64bit High Performance Multiplier with Redundant Binary Encoding | VLSI/2017 |
ENV2421 |
ENFIRE: A Spatio-Temporal Fine-Grained Reconfigurable Hardware | VLSI/2017 |
ENV2422 |
Hybrid Hardware/Software Floating-Point Implementations for Optimized Area and Throughput Tradeoffs | VLSI/2017 |
ENV2423 |
Efficient Soft Cancelation Decoder Architectures for Polar Codes | VLSI/2017 |
ENV2424 |
Low-Complexity Digit-Serial Multiplier Over GF(2m) Based on Efficient Toeplitz Block Toeplitz Matrix-Vector Product Decomposition | VLSI/2017 |
ENV2425 |
Sign-Magnitude Encoding for Efficient VLSI Realization of Decimal Multiplication | VLSI/2017 |
ENV2426 |
FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers over GF (2m) and Their Applications in Trinomial Multipliers | VLSI/2017 |
ENV2427 |
Low-Complexity Transformed Encoder Architectures for Quasi-Cyclic Non-binary LDPC Codes Over Subfields | VLSI/2017 |
ENV2428 |
Antiwear Leveling Design for SSDs With Hybrid ECC Capability | VLSI/2017 |
ENV2429 |
Energy-Efficient VLSI Realization of Binary64 Division with Redundant Number Systems Audio, Image and Video Processing | VLSI/2017 |
ENV2430 |
A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding | VLSI/2017 |
ENV2431 |
RoBA Multiplier: A Rounding-Based Approximate Multiplier for High-Speed yet Energy-Efficient Digital Signal Processing | VLSI/2017 |
ENV2432 |
Energy-Efficient Reduce-and-Rank Using Input-Adaptive Approximations | VLSI/2017 |
ENV2433 |
Dual-Quality 4:2 Compressors for Utilizing in Dynamic Accuracy Configurable Multipliers | VLSI/2017 |
ENV2434 |
An FPGA-Based Hardware Accelerator for Traffic Sign Detection | VLSI/2017 |
ENV2435 |
Soft Error Rate Reduction of Combinational Circuits Using Gate Sizing in the Presence of Process Variations | VLSI/2017 |
ENV2436 |
Time-Encoded Values for Highly Efficient Stochastic Circuits | VLSI/2017 |
ENV2437 |
Design of Power and Area Efficient Approximate Multipliers VERIFICATION | VLSI/2017 |
VERIFICATION |
||
ENV2438 |
COMEDI: Combinatorial Election of Diagnostic Vectors From Detection Test Sets for Logic Circuits | VLSI/2017 |
ENV2439 |
Reordering Tests for Efficient Fail Data Collection and Tester Time Reduction NETWORKING | VLSI/2017 |
NETWORKING |
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ENV2440 |
Multicast-Aware High-Performance Wireless Network-on-Chip Architectures | VLSI/2017 |
VLSI - BACK END PROJECT - TANNER(nm) / HSPICE(nm) / DSCH3 - MICROWIND(um) |
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ENV2441 |
Temporarily Fine-Grained Sleep Technique for Near- and Sub-threshold Parallel Architectures | VLSI/2017 |
ENV2442 |
Low-Power Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique | VLSI/2017 |
ENV2443 |
10T SRAM Using Half-VDD Precharge and Row-Wise Dynamically Powered Read Port for Low Switching Power and Ultralow RBL Leakage | VLSI/2017 |
ENV2444 |
Delay Analysis for Current Mode Threshold Logic Gate Designs | VLSI/2017 |
ENV2445 |
Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications | VLSI/2017 |
ENV2446 |
Probability-Driven Multi-bit Flip-Flop Integration With Clock Gating | VLSI/2017 |
ENV2447 |
A High-Speed and Power-Efficient Voltage Level Shifter for Dual-Supply Applications | VLSI/2017 |
ENV2448 |
A 0.1-2-GHz Quadrature Correction Loop for Digital Multiphase Clock Generation Circuits in 130-nm CMOS | VLSI/2017 |
ENV2449 |
Conditional-Boosting Flip-Flop for Near-Threshold Voltage Application | VLSI/2017 |
ENV2450 |
An All-MOSFET Sub-1-V Voltage Reference With a-51-dB PSR up to 60 MHz | VLSI/2017 |
ENV2451 |
A 65-nm CMOS Constant Current Source with Reduced PVT Variation | VLSI/2017 |
ENV2452 |
A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy | VLSI/2017 |
ENV2453 |
Preweighted Linearized VCO Analog-to-Digital Converter | VLSI/2017 |
ENV2454 |
A 100-mA, 99.11% Current Efficiency, 2-mVppRipple Digitally Controlled LDO with Active Ripple Suppression | VLSI/2017 |
ENV2455 |
Sense Amplifier Half-Buffer (SAHB): A Low-Power High-Performance Asynchronous Logic QDI Cell Template | VLSI/2017 |
ENV2456 |
On Micro-architectural Mechanisms for Cache Wear out Reduction | VLSI/2017 |
ENV2457 |
Energy-Efficient TCAM Search Engine Design Using Priority-Decision in Memory Technology | VLSI/2017 |
ENV2458 |
A 92-dB DR, 24.3-mW, 1.25-MHz BW Sigma-Delta Modulator Using Dynamically Biased Op Amp Sharing | VLSI/2017 |
ENV2459 |
A 0.45 V 147-375 nW ECG Compression Processor With Wavelet Shrinkage and Adaptive Temporal Decimation Architectures | VLSI/2017 |